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LAGUNA HILLS, Calif. - WisconsinEagle -- - Excellicon Inc. an advanced and innovative provider of end-to-end timing constraints products announced inclusion of its products into the Samsung foundry verification tool line up; SAFE™ (Samsung Advanced Foundry Ecosystem), as part of verified EDA solutions employed by Samsung foundry team dedicated to design and IP-verification services to help customers from early concept to large scale manufacturing.
Excellicon products are designed to simplify the timing constraints design process and shorten the design cycles by eliminating iterative constraints design and verification tasks. Generally, hand written constraints pose a high risk when it comes down to timing closure while missing a proper timing constraints definition can lead to potential chip failure and silicon respin.
ConMan (Constraints Manager), and ConCert (Constraints Certifier) are both designed to eliminate the risks and provide designers with insight and subjective information from early RTL stage to final tape-out about the state of chip timing requirements.
Other capabilities in Excellicon products can help to significantly help in efficiency of design flows by reducing the need for gate level sims, simulation of timing constraints, design of clock tree topology, and overall chip planning and verification process. The benefit is ability to perform early stage physical prototyping and timing impact for a high quality final tape-out from start to finish.
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"Having a robust reference design flow is crucial to success and timely chip tape-out. Samsung SAFE methodology will enable users to get their products to market faster and more efficiently" said Rick Eram, VP of sales and marketing at Excellicon.
He continued, "At Excellicon we believe by providing capabilities to design and verify the timing constraints from RTL to final tape-out will enable the same assurances on the timing side as those available for decades on the functional side of the design. By automating the design and verification of timing requirements we are enabling a significant upside in timing quality, performance and confidence level for designs handed off to Samsung foundry. Additionally, by eliminating communication and handoff gaps the overall design experience will be targeted and efficient. We are pleased with Samsung's decision for inclusion of our products in one of the most advanced design and foundry services and flows".
SAFE forum is held online on November 17th-18th of this year. Samsung Foundry and SAFE™ Partners will reveal solutions around designing next generation of Performance Platforms 2.0: Innovation, Intelligence, Integration. "This forum is designed to demonstrate how future designs using Samsung Foundry Technology will enable a seamless and collaborative environment for fastest time to market path for customers employing Samsung foundry design capabilities and products. Excellicon provides timing constraints design, validation and handoff as part of our Performance Platform 2.0 methodology" said Sangyun Kim, Vice President of Foundry Design Technology Team at Samsung Electronics
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About Excellicon
Excellicon is an innovative provider of end-to-end Timing Constraints Analysis and Debugging solutions for the automation of constraints authoring, completion, and validation from RTL to GDS with innovative analysis and debugging infrastructures. Excellicon products Constraints Manager, Constraints Certifier, Exception-ToolBox (ET), Budgeting-Tool Box (BT), Equivalence-Checker (EQ), ConTree, and ConStruct address the needs of designers at every stage of SOC design, planning and implementation in a unified end-2-end environment – Timing Closure; Done Once! Done Right!
www.excellicon.com
Excellicon products are designed to simplify the timing constraints design process and shorten the design cycles by eliminating iterative constraints design and verification tasks. Generally, hand written constraints pose a high risk when it comes down to timing closure while missing a proper timing constraints definition can lead to potential chip failure and silicon respin.
ConMan (Constraints Manager), and ConCert (Constraints Certifier) are both designed to eliminate the risks and provide designers with insight and subjective information from early RTL stage to final tape-out about the state of chip timing requirements.
Other capabilities in Excellicon products can help to significantly help in efficiency of design flows by reducing the need for gate level sims, simulation of timing constraints, design of clock tree topology, and overall chip planning and verification process. The benefit is ability to perform early stage physical prototyping and timing impact for a high quality final tape-out from start to finish.
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"Having a robust reference design flow is crucial to success and timely chip tape-out. Samsung SAFE methodology will enable users to get their products to market faster and more efficiently" said Rick Eram, VP of sales and marketing at Excellicon.
He continued, "At Excellicon we believe by providing capabilities to design and verify the timing constraints from RTL to final tape-out will enable the same assurances on the timing side as those available for decades on the functional side of the design. By automating the design and verification of timing requirements we are enabling a significant upside in timing quality, performance and confidence level for designs handed off to Samsung foundry. Additionally, by eliminating communication and handoff gaps the overall design experience will be targeted and efficient. We are pleased with Samsung's decision for inclusion of our products in one of the most advanced design and foundry services and flows".
SAFE forum is held online on November 17th-18th of this year. Samsung Foundry and SAFE™ Partners will reveal solutions around designing next generation of Performance Platforms 2.0: Innovation, Intelligence, Integration. "This forum is designed to demonstrate how future designs using Samsung Foundry Technology will enable a seamless and collaborative environment for fastest time to market path for customers employing Samsung foundry design capabilities and products. Excellicon provides timing constraints design, validation and handoff as part of our Performance Platform 2.0 methodology" said Sangyun Kim, Vice President of Foundry Design Technology Team at Samsung Electronics
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About Excellicon
Excellicon is an innovative provider of end-to-end Timing Constraints Analysis and Debugging solutions for the automation of constraints authoring, completion, and validation from RTL to GDS with innovative analysis and debugging infrastructures. Excellicon products Constraints Manager, Constraints Certifier, Exception-ToolBox (ET), Budgeting-Tool Box (BT), Equivalence-Checker (EQ), ConTree, and ConStruct address the needs of designers at every stage of SOC design, planning and implementation in a unified end-2-end environment – Timing Closure; Done Once! Done Right!
www.excellicon.com
Source: Excellicon
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